ASML’s maskless scanner is a matter of time

Shortly after 2000, ASML conducted extensive research into the viability of maskless lithography. With good reason. At that time, lithography for chips seemed to be running into a wall. Machines with calcium fluoride optics and 157nm laser sources were tough (and were scrapped in 2003), immersion was just emerging and EUV was still highly uncertain.

It’s hardly imaginable anymore, but a quarter century ago, there were fierce discussions about the technological-strategic direction in Veldhoven. Besides 157 nm, immersion and EUV, it also seemed like a good idea to investigate whether it would be economically attractive to project chip patterns (or parts thereof) pixel by pixel. After all, mask costs were rising exponentially and the number of interconnect layers was increasing.

By going maskless, chip manufacturers could also tap into interesting markets. Small series of ASICs would become viable. The technology might convince many FPGA customers to start printing cheap, faster, energy-efficient chips for clients.

So, ASML sought collaboration with Swedish Micronic, which would develop arrays of micromirrors for a maskless machine. Ultimately, however, the project ran aground. Veldhoven’s technological brain, Martin van den Brink, found it even more difficult than EUV at the time, mainly because of the high throughput demands.

Thus, the microprinter was shelved by ASML. Under the radar, research partner TNO kept working on it until back-end player Onto Innovation came a-knocking around 2020. This joint venture of Nanometrics and Rudolph (which brought in lithography and metrology), a successful supplier of steppers for the back-end, was interested in the technology, but no deal was struck.

No done deal

In the coming years, I think ASML will go maskless after all. Although it’s purely a gut feeling, there are good arguments for it. After 25 years of progress in computing power and memory, printing micropatterns with a powerful computer has become much more realistic. Even the relatively small EV Group announced last May a maskless computer-controlled microscanner for back-end packaging – see also the interview in Bits&Chips.

Add to that that ASML, under Christoph Fouquet, is thoroughly preparing for its new phase of life, an era in which its engineers are pushing boundaries in a different way. I wrote earlier about the challenges in industrialization and reliability. But now that we’re experiencing the economic end of Moore’s Law, the litho giant is working on adding value in other areas, such as process control (with its metrology systems and holistic approach). Since the announcement of the XT260 i-line scanner, it’s clear that it also has an eye on the back-end semiconductor chain. It’s currently positioning itself in the fast-growing advanced-packaging market (see my background story for a more comprehensive overview of the playing field). No one in the chip industry doubts that the future compute engines of data centers, PCs, servers, cars and so on will consist of highly integrated systems with very many chips. Those who succeed in delivering the machines that can flawlessly connect those ICs will be the winners.

Just as in the early days of maskless lithography, working with chiplets in advanced packaging is a simple idea, but very difficult to realize due to the high demands for precision and clean working. The major driving force here is the champion in IC production technology, TSMC. The Taiwanese foundry is currently implementing bonding technology in all kinds of AI systems for customers like Nvidia, Broadcom, Intel and AMD.

In the production of advanced packages, TSMC’s main suppliers ASML and Besi (with partner Applied Materials) are holding the best cards. However, this is certainly no done deal, especially not with TSMC’s past experiences with a monopolist in the most advanced lithography segment. In back-end litho, Canon is also an option. In wafer bonding, there are various competitors, including ASMPT and Japan’s TEL. Of course, a long customer relationship is worth something, but ultimately, all suppliers will have to prove themselves.

Top dollar

Why would maskless lithography be a strategically good move for ASML? First, because the company could already write 1-micron lines with it a quarter century ago. For comparison, Canon’s best back-end (mask-based) i-line steppers achieve 0.8 microns.

Second, there are a lot of big spenders in the AI market. The numbers aren’t large, but data centers pay top dollar for AI tiles. Besides Nvidia, AMD and Intel, the major hyperscalers are now developing their own AI chips and systems – all relatively small series that the Googles, Metas and Microsofts of this world demand be packaged as cheaply and reliably as possible. Working masklessly could well be the perfect way to create the interconnections between all those chiplets and chips in this market.

Top image credit: ASML