Creating signals with customized phase noise and jitter

How to use the IQ modulation capabilities of a vector signal generator to create signals with customized phase noise and jitter performance.

Dirk Faber

Various angle modulation schemes can be employed to alter the instantaneous phase of an RF signal and thereby control its jitter characteristics. Basic frequency modulation (FM) and phase modulation (PM) are useful for introducing simple, deterministic phase deviations and, equivalently, jitter. However, due to their deterministic nature, limited spectral complexity and inability to reproduce broadband or statistically correct jitter, they can’t emulate realistic oscillator phase noise.

Pseudorandom phase modulation, on the other hand, provides a powerful method for generating realistic, noise-like phase fluctuations that closely resemble the jitter and phase noise produced by physical oscillators, PLL synthesizers and other timing sources. Unlike basic FM or PM, which introduce only deterministic single-tone modulation, pseudorandom phase modulation can reproduce broadband noise, multi-corner spectral shapes, and statistically accurate jitter distributions. Using IQ modulation, a vector signal generator like Keysight’s AP504xA series can synthesize arbitrarily shaped phase noise profiles with high accuracy and repeatability.

Python script

At its core, IQ modulation allows the instantaneous phase of the RF carrier to be controlled by manipulating the signal’s in-phase (I) and quadrature (Q) components. By injecting carefully constructed I/Q waveforms containing noise-like phase variations, the output exhibits arbitrary and programmable phase noise spectra.

The pseudorandom phase sequence is produced digitally (eg via baseband waveform synthesis) and then translated into I and Q components. The vector signal generator uses these components to synthesize the RF output. The user controls the characteristics of the phase noise through parameters such as noise bandwidth, noise spectral slope (eg 1/f and 1/f²), corner frequencies (eg PLL loop bandwidth), broadband noise floor, RMS jitter and additional spurs or periodic artifacts (if desired).

Figure 1: Shaped phase noise in the 100 kHz to 100 MHz offset range, produced with IQ modulation data generated by the example script

Using a Python script, modulation data was generated that adds a phase noise bump to the intrinsic phase noise of an AP504xA (Figure 1). To evaluate the phase-noise shaping performance, two target phase-noise profiles were defined (Table 1). Pseudorandom phase modulation data was generated according to these patterns and applied as IQ modulation to a standard AP5041A outputting a 4 GHz RF carrier at 0 dBm. The resulting phase noise was measured using a Keysight E5058A SSA-X signal source analyzer (Figure 2).

Figure 2: E5058A phase noise measurement results (Tr 1: “high phase noise” pattern, Tr 2: AP5041A intrinsic phase noise, Tr 3: “low phase noise” pattern)

Figure 3: Comparison of measured data with the defined phase noise patterns

The measurements show that the pseudorandom phase modulation approach accurately reproduces the intended phase-noise profiles. As expected, the intrinsic phase noise of the AP5041A forms the lower limit of any achievable phase-noise shaping. Above this limit, arbitrary, user-defined phase-noise characteristics can be imposed on a real RF carrier signal with high fidelity. The achievable shaping performance is limited only by the intrinsic phase noise of the AP504xA, the 200 MHz single-sideband IQ-modulation bandwidth of the AP504xA and the length of the IQ waveform, which determines the minimum realizable offset frequency.

System robustness

This demonstrates how the IQ modulation capabilities of a vector signal generator can be used to create signals with customized phase noise and jitter performance. By intentionally degrading phase noise (or equivalently, jitter), the phase noise behavior of real-world clock or LO sources can be accurately replicated, specific phase noise profiles can be modeled, such as those produced by PLL synthesizers, and system robustness can be tested under controlled jitter degradation and worst-case timing conditions. These techniques allow engineers to emulate realistic operating environments and validate system performance without requiring multiple physical reference sources.