ASML, TSMC and Imec have demonstrated a scalable 300mm manufacturing flow for 2D-material transistors, marking a step toward industrial adoption of post-silicon logic devices. Presented at the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, the work delivers both nFETs and pFETs with a contacted poly pitch of 50nm on the same 300mm wafer. According to the partners, this is the first time complementary 2D transistors have been realized at such dimensions using an industry-compatible process.
Because of their favorable electrical properties, atomically thin layers of transition metal dichalcogenides, such as MoS2, WS2 and WSe2, have long been considered promising candidates to succeed silicon as the channel material in CMOS transistors. However, translating laboratory demonstrations into manufacturable processes has proven a major challenge.
The new process may have cracked that problem. It combines a CMOS-like integration scheme with EUV lithography and an unconventional reverse thin-film transistor architecture. The transistors are built on pre-patterned tungsten contacts, after which the 2D channel material is transferred and covered by an overlapping deposited gate. The approach enabled channel lengths down to 28nm while maintaining low leakage currents and achieving a reported 94 percent yield of operational devices.
