In ASML’s annual report, CEO Christophe Fouquet identifies cost reduction as a key priority for 2025 and beyond. “Our customers face a lot of difficult choices in the next few years – and they have to make sure that the technology they choose can deliver the outcomes they need. We’re aware that the move to the next technology in our lithography systems could potentially come with very high costs for our customers. Our task – and our opportunity – is to understand how we can help them (…) achieve their quality goals at the lowest possible risk and the lowest possible cost,” Fouquet states in the report published on 5 March.
Key challenges for the semiconductor industry – other than man-made ones such as tariffs – include continued shrink and the rise of 3D ICs, along with the concomitant escalation of complexity in design and manufacturing, and lowering greenhouse gas emissions and the use of harmful chemicals.
At ASML’s Investor Day last October, Fouquet and other speakers laid out some of the firm’s strategies to lower costs for chipmakers. In 2D integration, ASML will be introducing a cost-saving common platform for low-NA, high-NA and possibly hyper-NA EUV systems, featuring increased throughput of up to 500 wafers per hour. In 3D ICs, the litho giant sees a role for itself in compensating for mechanical deformations as a result of wafer bonding.
