Light has touched a resist-coated wafer in ASML’s first operational high-NA EUV tool in Veldhoven. The milestone was made public by Intel’s general manager for technology development, Ann Kelleher, during a keynote presentation at the SPIE Advanced Lithography conference, and confirmed by ASML. Previously, it was announced that the High-NA Lab in Veldhoven, co-run by ASML and Imec, will be ready to receive customers later in Q1.
The dummy exposure – there was no actual patterning being performed – is one of many key stages in the installation of a new scanner, though a highly symbolic one. ASML’s systems are highly modular, and each module is validated individually before assembly of the ensemble. Source, projection optics and so on were therefore already known to work. The current focus is on calibrating the tool, an ASML spokesperson told Tom’s Hardware.
This article is exclusively available to premium members of Bits&Chips. Already a premium member? Please log in. Not yet a premium member? Become one for just €20 for the first year and enjoy all the benefits.
