High EUV double-patterning cost prompted TSMC to delay the introduction and ramp of 3nm chips, according to an EE Times report. Loosening design rules didn’t prove a viable alternative, as this inflated die size too much. The N3 ramp isn’t expected to reach full potential before TSMC has ASML’s NXE:3800E systems up and running, whose 33-percent gain in throughput ease the pain of double patterning.
N3 entered volume production in Q4 2022, but won’t start contributing to wafer revenue until this year’s third quarter, TSMC told analysts during an earnings call discussing Q1 2023 results. It’s generally understood that a large share of the foundry’s initial production runs are for the benefit of Apple, which is willing to adopt new nodes as soon as they’re available. Most other companies wait for TSMC’s relaxed N3E process, which is scheduled for introduction in H2 2023.
“TSMC will accelerate the adoption of the NXE:3800E in the first half of 2024 as the foundry scales N3E and other variations of the 3nm node for more customers,” EE Times cites Mehdi Hosseini, research analyst at Susquehanna.
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