Silicon goes vertical with rollable transistor layers

Researchers at the University of Illinois Urbana-Champaign have devised a method to manufacture monolithic 3D silicon circuits constructed from stacked silicon nanomembranes. The approach reduced the footprint of the IC up to three times compared to the 2D equivalent while maintaining the silicon-crystal quality needed to construct high-performance devices.

One of the key challenges in building transistor layers on top of existing circuitry is the thermal budget. Temperatures exceeding about 400 degrees Celsius damage the layers below. Most experimental monolithic 3D technologies have therefore relied on alternative semiconductor materials, including metal oxides, carbon nanotubes and two-dimensional materials, which can be processed at lower temperatures. Due to their subpar performance compared to silicon, however, the advantages of vertical integration tend to be underwhelming.