Imec has proposed a new transistor architecture to bridge the transition from gate-all-around (GAA) FETs to CFETs. The outer wall forksheet device serves as an alternative to the regular forksheet, for which manufacturability concerns lingered.
Imec’s current roadmap schedules the introduction of the vertically stacked nMOS-pMOS CFET architecture at the A7 node, which will see the light after 2030. With N2 going into high-volume production this year, also marking the debut of GAA technology, this leaves two more GAA nodes: A14 and A10. The forksheet transistor, featuring an isolating dielectric wall between adjacent nMOS and pMOS devices, was intended to improve the scalability potential of GAA technology, primarily at the A10 node.
Despite wafer-scale forksheet manufacturability demonstrations by Imec, chipmakers weren’t convinced. They remained particularly concerned about the manufacturability of the inner wall, which needs to be very thin but is also fabricated early in the process flow, exposing the structure to many steps that could damage it.
At the 2025 Symposium on VLSI Technology and Circuits, this week in Kyoto, Imec researchers presented the novel forksheet device architecture, which places the dielectric wall at the standard cell boundary, turning it into a p-p or n-n wall (via EE Times). This design features reduced process complexity and superior performance while preserving area scalability, Imec claims.
Imec is currently investigating how the outer wall forksheet design can be applied to the CFET architecture.
