Imec has established the baseline manufacturing process for a silicon interposer platform on Europe’s NanoIC pilot line. The process will underpin a design kit scheduled for release in early 2027. Universities, start-ups and fabless chip companies will be able to use the kit to explore interposer designs in Cadence and Synopsys software.
A silicon interposer sits beneath the dies in a package, providing short, densely spaced connections between components such as compute chiplets and high-bandwidth memory. Imec’s platform combines multiple metal routing layers with through-silicon vias and supports microbump pitches as small as 20 micrometers. The design kit will let engineers assess how those features fit their package designs before committing to fabrication.
The kit will complement two interconnect options that are already available through NanoIC: one for fine-pitch redistribution-layer (RDL) interposers, which offer a lower-cost routing option, and one for die-to-wafer hybrid bonding, which enables denser direct connections between dies.
“By providing a common technology foundation for advanced interconnect technologies and making them accessible through advanced PDKs, NanoIC enables researchers, start-ups and fabless companies to experiment with the different interconnect approaches, evaluate future system architectures and build expertise in advanced packaging. In doing so, it helps Europe, and its strategic European markets, prepare for the next generation of physical AI, automotive and advanced computing systems,” comments Bart Placklé, Senior Vice President of Automotive Technologies at Imec.
