High-NA EUV scanners can pattern the most challenging layers in A14 and A10 logic chips in a single exposure, when low-NA EUV would require 3-4 masks, Imec reports. Similar benefits apply to future DRAM generations, where key multi-patterned layers at 32nm D1d and 28nm D0a nodes could move to single-patterning flows.
The simplification is central to the economics of next-generation chip production. Every eliminated mask removes additional process loops, overlay corrections and defect opportunities, reducing both cost and cycle time. For the time being, however, TSMC is holding off on high-NA until at least the A12 node, apparently prioritizing manufacturing maturity and predictable ramp schedules over expedited adoption of the latest litho tooling.
Imec said that ongoing R&D work for high-NA includes depth-of-focus improvement, stochastic defect mitigation and stitching enablement. Depth of focus is the ‘zone’ in which a sharp image is projected, which becomes smaller as the numerical aperture increases. Stochastic defects refer to random printing failures, such as missing or bridged features caused by the limited number of EUV photons reaching the resist at extremely small dimensions. Stitching addresses the smaller exposure field of high-NA scanners, where large chip layouts may need to be split across multiple exposures.
