Researchers at Eindhoven University of Technology (TUE) and partners in the European Convolve project have developed and validated a new AI chip architecture aimed at bringing energy-efficient edge computing to laptops, smartphones and other devices. Rather than relying on power-hungry cloud data centers, the prototype executes AI workloads locally, reducing energy consumption, latency and dependence on remote infrastructure. The team presented its results at this year’s ESSERC conference in Spain.
The project’s key innovation is a cross-layer design methodology that jointly optimizes AI algorithms, processor architecture, memory systems and circuit design instead of treating them as separate development steps. The resulting Chimera prototype combines programmable RISC-V processors with specialized AI accelerators, including memory-centric and neuromorphic computing techniques, to minimize costly data movement.
According to the researchers, measurements on fabricated chips using real AI workloads confirmed improvements in energy efficiency while maintaining performance and accuracy. “To prove we had succeeded in achieving those goals, we evaluated prototype chips we had fabricated, rather than simulations alone. Our team applied realistic AI workloads to the chip, so we could really see how well it performed. We measured energy efficiency, throughput, latency, silicon area and application accuracy and compared the results with relevant existing designs, which proved our point,” says lead researcher Manil Dev Gomony, professor of low-power digital hardware design at TUE.
