Dai Nippon Printing (DNP) has developed a nanoimprint lithography (NIL) template with 10-nanometer line width, supporting the production of 1.4nm-class logic semiconductors. The new template could “replace a portion of the EUV lithography process,” the Japanese firm claims.
DNP has been developing NIL templates since 2003 and is working with Canon, which has launched a NIL tool for advanced chipmaking, although the latter firm isn’t mentioned in DNP’s press release. Canon’s claims of NIL being able to go head-to-head with EUV have been met with skepticism.
Like Canon, DNP positions its 10nm template as a way to reduce manufacturing costs and environmental burden, especially for chipmakers without access to EUV infrastructure. It has started evaluation work with semiconductor clients and plans to begin mass production in 2027, aiming for NIL template sales of 4 billion yen (about 22 million euros) in fiscal year 2030.
