Imec showcased progress in 2D semiconductor integration, reporting record pFET performance using monolayer WSe2 and demonstrating fab-compatible modules for gate and contact formation. The work, which was conducted in partnership with Intel and TSMC, was presented at this year’s IEEE IEDM.
Most 2D FET efforts to date have focused on n-type devices based on MoS2 or WS2. For fully 2D-material-based CMOS to materialize, R&D on pFETs needs to catch up. The hole-conducting counterparts require different channel materials and therefore present new challenges for making contacts and gate stacks.
Imec used a WSe2 bilayer made by TSMC. “We then oxidized the top WSe2 monolayer, converting it into an interfacial layer that successfully supported the deposition of the HfO2 gate oxide. This fab-compatible lab-based integration approach resulted in record performance of our dual-gated pFETs,” explains Imec’s Gouri Sankar Kar.
Separately, Imec and Intel developed a 300mm module for forming damascene-style top contacts on both n-type and p-type 2D FETs. A selective oxide etch removed multiple dielectric layers, including a laterally etched AlOx interfacial layer, reducing the equivalent oxide thickness (EOT) of the gate stack. This contributes to improved transfer characteristics and reinforces the feasibility of vertical contact schemes in a manufacturable flow.
