The European NanoIC pilot line, coordinated by Imec, has released two new process design kits (PDKs) to support early exploration of next-generation semiconductor technologies. The A14 pathfinding PDK provides a virtual design environment for advanced logic scaling at the 14A node, introducing a direct backside contact architecture that improves area efficiency and reduces power compared with earlier nodes. The EDRAM system exploration PDK enables designers to study dense, low-latency embedded memory architectures that bridge the gap between off-chip DRAM and on-chip SRAM for data-intensive and AI applications.
Both PDKs are accessible through Europractice and give researchers, startups and industry teams early access to realistic design rules, implementation flows and libraries long before actual hardware is available. The releases aim to lower barriers to innovation in logic and memory scaling, helping developers anticipate integration challenges and benchmark designs against emerging technology metrics.
