Samsung Electronics is aiming to adopt the forksheet transistor architecture at the 1nm node, according to the Korea Economic Daily. An extension of gate-all-around (GAA) technology that’s used in all 2nm processes, the forksheet increases density by pushing NMOS and PMOS transistors closer together. If confirmed, Samsung would be the first leading-edge chip manufacturer to commit to the transistor design in volume manufacturing.
The conceptual successor of the GAA transistor is the complementary FET (CFET), which stacks NMOS and PMOS on top of each other. As explained by Imec, however, CFET mass production isn’t likely to happen before the A7 node, while extending GAA until at least the A10 generation is challenging. “This is where the forksheet device architecture may bring relief, a non-disruptive technology with larger scaling potential than regular GAA nanosheet technology,” Imec wrote.
Forksheet technology builds on gate-all-around by inserting dielectric walls between adjacent nanosheet transistors. By effectively reclaiming unused area between devices, the structure increases transistor density without compromising performance.
